Architecture for fast content addressable memory search

ABSTRACT

A search pattern is generated based on an input search word comprising a first sequence of bits. The search pattern comprises a first set of signals representing the input search word and a second set of signals representing a second sequence of bits comprising an inverse of the first sequence of bits. The search pattern is provided as input to search lines of a content addressable memory (CAM) block. The search pattern causes at least one string in the CAM block to be conductive and provide a signal to a page buffer connected to the string in response to the input search word matching a data entry stored on the string. A location of the data entry is determined based on data read from the page buffer and the location is output.

PRIORITY APPLICATION

This application is a continuation of U.S. application Ser. No. 16/727,671, filed Dec. 26, 2019, which is incorporated herein by reference in its entirety.

TECHNICAL FIELD

Embodiments of the disclosure relate generally to memory sub-systems, and more specifically, relate to a memory device architecture to facilitate a fast content addressable memory (CAM) search.

BACKGROUND

A memory sub-system can include one or more memory devices that store data. The memory devices can be, for example, non-volatile memory devices and volatile memory devices. In general, a host system can utilize a memory sub-system to store data at the memory devices and to retrieve data from the memory devices.

BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure.

FIG. 1 illustrates an example computing system that includes a content addressable memory (CAM) architecture implemented within a memory sub-system, in accordance with some embodiments of the present disclosure.

FIG. 2 is a block diagram illustrating additional details of the CAM architecture implemented within the memory sub-system, in accordance with some embodiments of the present disclosure.

FIG. 3 illustrates components of a CAM block implemented within a memory device in the exemplary form of a NAND-type flash memory device, in accordance with some embodiments of the present disclosure.

FIG. 4 illustrates a single CAM cell of the CAM block implemented within the NAND flash memory device, in accordance with some embodiments of the present disclosure.

FIG. 5 is a block diagram illustrating a shift register, which may be included as part of the CAM architecture, in accordance with some embodiments of the present disclosure.

FIG. 6 is a flow chart illustrating example operations of the memory sub-system in performing a CAM search, in accordance with some embodiments of the present disclosure.

FIG. 7 is a block diagram of an example computer system in which embodiments of the present disclosure may operate.

DETAILED DESCRIPTION

Aspects of the present disclosure are directed to content addressable memory (CAM) architecture for a memory sub-system. A memory sub-system can be a storage device, a memory module, or a hybrid of a storage device and memory module. Examples of storage devices and memory modules are described below in conjunction with FIG. 1. In general, a host system can utilize a memory sub-system that includes one or more components, such as memory devices that store data. The host system can provide data to be stored at the memory sub-system and can request data to be retrieved from the memory sub-system. A memory sub-system controller typically receives commands or operations from the host system and converts the commands or operations into instructions or appropriate commands to achieve the desired access to the memory components of the memory sub-system.

A content addressable memory is a special type of memory device that is used in certain very high speed searching applications such as identifier (ID) and pattern matching. Generally, a CAM is searched by comparing input search data against a table of stored data entries and a memory address of matching data in the table is returned. CAMs are frequently implemented in dynamic random-access memory (DRAM), or synchronous random-access memory (SRAM). However, both DRAM and SRAM have a limited memory capacity, which limits the amount of data that can be stored and searched in conventional CAM implementations.

A conventional negative- and (NAND)-type flash memory device may comprise one or more blocks. A NAND block comprises a two-dimensional (2-D) array comprising pages (rows) and strings (columns). A three-dimensional (3D) NAND-type flash memory device comprises multiple planes, each of which comprises one or more blocks. A string comprises a plurality of single NAND flash cells (also referred to hereinafter simply as “memory cells”) connected in series. A single NAND flash cell comprises a transistor that stores an electric charge on a memory layer that is isolated by oxide insulating layers above and below. Generally, when there is a charge on the memory layer of a memory cell, the memory cell is programmed and recognized by a memory sub-system as a binary value of 0. When the memory layer of a memory cell has no charge, it is erased and recognized as a binary value of 1.

A string is a unit in a NAND-type flash memory device. NAND-type flash components typically have 32 or more memory cells. Conventionally, each memory cell is used to represent a bit value (0 or 1). Thus, in conventional implementations, a string with 32 memory cells can represent 32 bits of data and a string with 64 memory cells can represent 64 bits of data.

In a NAND-type flash memory block, individual strings are connected to allow storage and retrieval of data from selected cells. Typically, strings in the block are connected at one end to a common source line and at the other end to a bit line. Each string also contains two control mechanisms in series with the memory cells. String and ground select transistors are connected to the string select line and ground select line. Memory cells in NAND-type flash components are connected horizontally at their control gates to a word line to form a page. A page is a set of connected memory cells that share the same word line and are the minimum unit to program. NAND-type flash memory devices may have page sizes of 64K or 128K cells. Although conventional NAND-type flash memory has a larger capacity than DRAM and SRAM, it is generally too slow for serial data searching and access.

Aspects of the present disclosure address the foregoing and other issues with a CAM architecture implemented in a NAND-type flash memory device to provide both fast and high capacity search capability. Consistent with this architecture, data entries are stored on strings of a NAND-type flash memory array. Contrary to conventional NAND implementations, each bit of a data entry is mapped to a pair of memory cells that are configured to be complementary. That is, a first memory cell of the pair stores a bit value and a second memory cell of the pair stores an inverse of the bit value. A search pattern representing an input search word is input vertically on each word line corresponding to a string in the array. A single read operation compares the input search word with all strings in the array and identifies a storage address of matching data.

A NAND-based CAM architecture, as described herein, enables new applications where high speed and high-density pattern matching is required, such as applications related to artificial intelligence, machine vision, and large genetic databases. Such a CAM architecture also improves existing databased search systems and search algorithms such as index memories in cloud networking and servers.

FIG. 1 illustrates an example computing system 100 that includes a memory sub-system 110, in accordance with some embodiments of the present disclosure. The memory sub-system 110 can include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of such.

A memory sub-system 110 can be a storage device, a memory module, or a hybrid of a storage device and memory module. Examples of a storage device include a SSD, a flash drive, a universal serial bus (USB) flash drive, an embedded Multi-Media Controller (eMMC) drive, a Universal Flash Storage (UFS) drive, a secure digital (SD) card, and a hard disk drive (HDD). Examples of memory modules include a dual in-line memory module (DIMM), a small outline DIMM (SO-DIMM), and various types of non-volatile dual in-line memory module (NVDIMM).

The computing system 100 can be a computing device such as a desktop computer, laptop computer, network server, mobile device, a vehicle (e.g., airplane, drone, train, automobile, or other conveyance), Internet of Things (IoT) enabled device, embedded computer (e.g., one included in a vehicle, industrial equipment, or a networked commercial device), or such computing device that includes memory and a processing device (e.g., a processor).

The computing system 100 can include a host system 120 that is coupled to one or more memory sub-systems 110. In some embodiments, the host system 120 is coupled to different types of memory sub-systems 110. FIG. 1 illustrates one example of a host system 120 coupled to one memory sub-system 110. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect communicative connection or direct communicative connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical, optical, magnetic, and so forth.

The host system 120 can include a processor chipset and a software stack executed by the processor chipset. The processor chipset can include one or more cores, one or more caches, a memory controller (e.g., NVDIMM controller), and a storage protocol controller (e.g., PCIe controller, SATA controller). The host system 120 uses the memory sub-system 110, for example, to write data to the memory sub-system 110 and read data from the memory sub-system 110.

The host system 120 can be coupled to the memory sub-system 110 via a physical host interface, a double data rate (DDR) memory bus. Small Computer System Interface (SCSI), a dual in-line memory module (DIMM) interface (e.g., DIMM socket interface that supports Double Data Rate (DDR)), Open NAND Flash Interface (ONFI), Double Data Rate (DDR), Low Power Double Data Rate (LPDDR), and so forth. The physical host interface can be used to transmit data between the host system 120 and the memory sub-system 110. The host system 120 can further utilize an NVM Express (NVMe) interface to access components (e.g., memory devices 130) when the memory sub-system 110 is coupled with the host system 120 by the PCIe interface. The physical host interface can provide an interface for passing control, address, data, and other signals between the memory sub-system 110 and the host system 120. FIG. 1 illustrates a memory sub-system 110 as an example. In general, the host system 120 can access multiple memory sub-systems via a same communication connection, multiple separate communication connections, and/or a combination of communication connections.

The memory devices 130,140 can include any combination of the different types of non-volatile memory devices and/or volatile memory devices. The volatile memory devices (e.g., memory device 140) can be, but are not limited to, random access memory (RAM), such as dynamic random-access memory (DRAM) and synchronous dynamic random-access memory (SDRAM).

Some examples of non-volatile memory devices (e.g., memory device 130) includes a NAND type flash memory and write-in-place memory, such as a three-dimensional cross-point (“3D cross-point”) memory device, which is a cross-point array of non-volatile memory cells. A cross-point array of non-volatile memory can perform bit storage based on a change of bulk resistance, in conjunction with a stackable cross-gridded data access array. Additionally, in contrast to many flash-based memories, cross-point non-volatile memory can perform a write in-place operation, where a non-volatile memory cell can be programmed without the non-volatile memory cell being previously erased. NAND type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

Each of the memory devices 130 can include one or more arrays of memory cells. One type of memory cell, for example, single level cells (SLC) can store one bit per cell. Other types of memory cells, such as multi-level cells (MLCs), triple level cells (TLCs), and quad-level cells (QLCs), can store multiple bits per cell. In some embodiments, each of the memory devices 130 can include one or more arrays of memory cells such as SLCs, MLCs, TLCs, QLCs, or any combination of such. In some embodiments, a particular memory device can include an SLC portion, and an MLC portion, a TLC portion, or a QLC portion of memory cells. The memory cells of the memory devices 130 can be grouped as pages that can refer to a logical unit of the memory device used to store data. With some types of memory (e.g., NAND), pages can be grouped to form blocks.

Although non-volatile memory devices such as NAND type flash memory (e.g., 2D NAND, 3D NAND) and 3D cross-point array of non-volatile memory cells are described, the memory device 130 can be based on any other type of non-volatile memory, such as read-only memory (ROM), phase change memory (PCM), self-selecting memory, other chalcogenide based memories, ferroelectric transistor random-access memory (FeTRAM), ferroelectric random access memory (FeRAM), magneto random access memory (MRAM), Spin Transfer Torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

As shown, any one of more of the memory devices 130 may be configured to include one or more content addressable memory (CAM) blocks 112. A CAM block 112 comprises one or more arrays of memory cells organized as strings. Each string stores a data entry and comprises memory cells connected in series between a match line and a page buffer. That is, the CAM block 112 comprises multiple match lines and each match line is connected to one of multiple strings in an array. The match lines of the CAM block 112 correspond to bit lines of the NAND block on which the CAM block 112 is implemented. Within a given string, memory cells are organized as complementary memory cell pairs. Each bit value of the data entry stored by a string is mapped to one of the complementary memory cell pairs in the string.

The CAM block 112 can be searched by providing a search pattern as input to search lines of the CAM block 112. The search lines of the CAM block 112 correspond to word lines of the NAND block on which the CAM block 112 is implemented. The match lines of the CAM block 112 are precharged to facilitate searching. That is, prior to input of the search, a voltage signal is applied to the match lines of the CAM block 112. During a search operation, if the input search word matches any data entry stored by the CAM block 112, one or more matched lines (e.g., match lines corresponding to strings storing the matching data entry) become conductive and discharge a signal in response to the search pattern input at the search lines. If the search word does not match any stored entry, all match lines are non-conductive. Each match line is further connected to a page buffer (e.g., comprises one or more latch circuits) that receives a discharge signal and stores data indicating that matched data is stored along the connected match line.

A memory sub-system controller 115 (or controller 115 for simplicity) can communicate with the memory devices 130 to perform operations such as reading data, writing data, or erasing data at the memory devices 130 and other such operations. The memory sub-system controller 115 can include hardware such as one or more integrated circuits and/or discrete components, a buffer memory, or a combination thereof. The hardware can include digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory sub-system controller 115 can be a microcontroller, special purpose logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.

The memory sub-system controller 115 can include a processor 117 (e.g., processing device) configured to execute instructions stored in a local memory 119. In the illustrated example, the local memory 119 of the memory sub-system controller 115 includes an embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines that control operation of the memory sub-system 110, including handling communications between the memory sub-system 110 and the host system 120.

In some embodiments, the local memory 119 can include memory registers storing memory pointers, fetched data, and the like. The local memory 119 can also include ROM for storing micro-code. While the example memory sub-system 110 in FIG. 1 has been illustrated as including the memory sub-system controller 115, in another embodiment of the present disclosure, a memory sub-system 110 does not include a memory sub-system controller 115, and can instead rely upon external control (e.g., provided by an external host, or by a processor or controller separate from the memory sub-system).

In general, the memory sub-system controller 115 can receive commands or operations from the host system 120 and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory devices 130. The memory sub-system controller 115 can be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error-correcting code (ECC) operations, encryption operations, caching operations, and address translations between a logical address (e.g., logical block address (LBA), namespace) and a physical address (e.g., physical block address) that are associated with the memory devices 130. The memory sub-system controller 115 can further include host interface circuitry to communicate with the host system 120 via the physical host interface. The host interface circuitry can convert the commands received from the host system into command instructions to access the memory devices 130 and convert responses associated with the memory devices 130 into information for the host system 120.

The memory sub-system 110 can also include additional circuitry or components that are not illustrated. In some embodiments, the memory sub-system 110 can include a cache or buffer (e.g., DRAM) and address circuitry (e.g., a row decoder and a column decoder) that can receive an address from the memory sub-system controller 115 and decode the address to access the memory devices 130.

In some embodiments, the memory devices 130 include local media controllers 135 that operate in conjunction with memory sub-system controller 115 to execute operations on one or more memory cells of the memory devices 130. An external controller (e.g., memory sub-system controller 115) can externally manage the memory device 130 (e.g., perform media management operations on the memory device 130). In some embodiments, a memory device 130 is a managed memory device, which is a raw memory device combined with a local controller (e.g., local controller 135) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

The memory sub-system 110 also includes a search component 113 that facilitates searching of CAM block 112. Consistent with some embodiments, the search component 113 is included in the in the memory device 130, as shown. In some embodiments, the controller 115 includes at least a portion of the search component 113. For example, the controller 115 can include the processor 117 (processing device) configured to execute instructions stored in the local memory 119 for performing the operations of the search component 113 described herein. In some embodiments, the search component 113 is part of the host system 120, an application, or an operating system.

The search component 113 generates a search pattern based on a received input search word and inputs the search pattern vertically along search lines the CAM block 112. If a data entry matching the input search word is stored by the CAM block 112, the search pattern causes a match line storing the data entry (also referred to as a “matched line”) to become conductive and since the match lines are precharged, a matched line provides a signal to a connected page buffer that indicates that the search word is stored thereon. A location (e.g., a storage address) of any matching data entry may be identified based on the signal provided by the matched line as a result of the string being conductive. More specifically, a page buffer connected to any matched line stores a datum in response to detecting a discharge signal that indicates that the matched datum is stored along the matched line. A component of the search component 113 (e.g., a read-out circuit) may read data from the page buffer. Based on the data read from the page buffer, the search component 113 outputs an indication of whether the search word is stored by the CAM block 112 and an indicator of the location of the match line.

FIG. 2 is a block diagram illustrating additional details of the CAM architecture implemented within the memory sub-system 110, in accordance with some embodiments of the present disclosure. As shown in FIG. 2, a memory device 200 may be organized into multiple planes—planes 201-1 to 201-4. The memory device 200 is an example of one of the memory device 130. Although FIG. 2 illustrates the memory device 200 as comprising four planes, it shall be appreciated that the memory device 200 is not limited to four planes, and in other embodiments, may comprise more or fewer planes. Each of the planes 201-1 to 201-4 are configured to include one or more CAM blocks 112. The number of CAM blocks 112 per plane may be configured via software or hardware.

As shown, the search component 113 receives an input search word 206 and generates a search pattern 208 based on the input search word 206. The input search word 206 comprises a first sequence of bits (e.g., “1011”). The search pattern 208 generated by the search component 113 comprises a first set of voltage signals 209A (SL_(0-M)) representing the input search word and a second set of voltage signals 209B (SL _(0-M)) representing a second sequence of bits comprising an inverse of the first sequence of bits (e.g., “010)”). The search component 113 comprises an inverter 210 to generate an inverse of the input search word and a level selector 211 to generate the first and second signals. In generating the first and second voltage signals, the level selector 211 may use voltage V_(high) to represent a binary value of “1” and use a voltage V_(low) to represent a binary value of “0” where V_(high) is above a threshold voltage (Vt) and V_(low) is below it.

To search one of the CAM blocks 112, the search component 113 inputs the search pattern 208 vertically along search lines of the one of the CAM blocks 112 being searched. Input of the search pattern 208 causes any complementary memory cell pairs representing a matching stored bit value to become conductive. If a string is storing matching data, the entire string becomes conductive. Match lines in the CAM block 112 are precharged (e.g., connected to V_(high)), and because the match lines are precharged, input of the search pattern 208 on the search lines causes any match lines in the block that are storing matching data (e.g., a data entry that is identical to the search word 206) to output a discharge signal because the corresponding string is conductive. The discharge signal provides an indication that matching data (e.g., the input search word 206) is stored thereon. The discharge signal provides an indication that matching data is stored on the string connected to the match line.

Each string is connected between a match line and a page buffer (e.g., comprising one or more latch circuits) and the page buffer of a matched line stores data indicating matching data is stored along the matched line in response to the signal provided as a result of the match line discharging along the string. As shown, plane 201-4 includes page buffer(s) 212. A page buffer 212 may comprise one or more latch circuits. Physically, the page buffer(s) 212 reside under or adjacent to the arrays of memory cells in which CAM block(s) 112 are implemented. A page buffer 212 latches data based on the signal provided by a matched line when matching data is stored by the connected string that conducts the signal to the page buffer 212. The search component 113 reads data from the page buffer(s) 212 and provides an indicator of whether the input search word 206 is stored in the one of the CAM blocks 112 being searched as output along with a location of the matching data (e.g., a memory address of the string in the array).

In some embodiments, the search component 113 may sequentially search for matching data in the CAM block(s) 112 of the planes 201-1 to 201-4. That is, the search component 113 may initially search CAM block(s) 112 of the plane 201-1, thereafter search CAM block(s) 112 of the plane 201-2, thereafter search CAM block(s) 112 of the plane 201-3, and finally search CAM block(s) 112 of the plane 201-4.

In some embodiments, the search component 113 may search for matching data in the CAM block(s) 112 of the planes 201-1 to 201-4 in parallel. That is, the search component 113 may simultaneously search all CAM block(s) 112 of the planes 201-1 to 201-4 to find matching data. Parallel searching of the planes 201-1 to 201-4 allows all data entries stored among all CAM block(s) 112 of the planes 201-1 to 201-4 to be searched in a single search operation rather than completing the search of all data entries in four separate search operations. Hence, parallel searching, as utilized in the embodiments described above, may allow the search component 113 to achieve an increase to search speed relative to embodiments in which sequential searching is utilized.

In some embodiments, data entries may be stored across two or more of the planes 201-1 to 201-4. In these instances, the search component 113 may simultaneously search for portions of matching data across two or more of the planes 201-1 to 2014. Dividing data entries across planes allows for greater word size when compared to embodiments in which data entries are stored within a single plane. For example, if each of the CAM blocks 112 supports 64-bit words, dividing the data entries among all four planes would allow the memory device 200 to support 256-bit words (4*64=256).

To avoid obscuring the inventive subject matter with unnecessary detail, various functional components that are not germane to conveying an understanding of the inventive subject matter have been omitted from FIG. 2. However, a skilled artisan will readily recognize that various additional functional components may be included as part of the memory sub-system 110 to facilitate additional functionality that is not specifically described herein. For example, the memory sub-system 110 may comprise additional circuitry (e.g., one or more multiplexers) that allows for conventional read and write operations to be performed with respect to any one of more of the memory device 130.

FIG. 3 illustrates components of a CAM block 300 implemented within the memory device 130 in the exemplary form of a NAND-type flash memory device, in accordance with some embodiments of the present disclosure. The CAM block 300 is an example of the CAM block 112.

As shown, the CAM block 300 comprises match lines 302-0 to 302-N, search lines 304-0 to 304-M, and inverse search lines 306-0 to 306-M. In this implementation, the match lines 302-0 to 302-N of the CAM block 300 correspond to bit lines of the NAND-type flash memory device and the search lines 304-0 to 304-M and inverse search lines 306-0 to 306-M of the CAM block 300 correspond to word lines of the NAND-type flash memory device.

Each of the match lines 302-0 to 302-N is connected to a string comprising a plurality of memory cells connected in series. For example, match line 302-0 is connected to a string comprising memory cells 308-0 to 308-X, where X=2M. Memory cells in each string of the CAM block 300 are configured to be complementary pairs. For example, with the string connected to match line 302-0, memory cells 308-0 to 308-X are programmed as complementary memory cell pairs 310-0 to 310-M.

Memory cell pairs are configured to be complementary in that one memory cell in the pair stores a data value (“0”) and the other memory cell in the pair stores an inverse of the data value (“1”). For example, as shown in FIG. 4, memory cell pair 310-0 (CAM cell) comprises two memory cells 308-0 and 308-1. Memory cell 308-0 stores a data bit value DATA, and memory cell 308-1 stores DATA, which is an inverse of the data bit value DATA. Also, as shown, search line 304-0 is connected to a control gate of the memory cell 308-0 and inverse search line 306-0 is connected to a control gate of the memory cell 308-1.

Search line 304-0 receives a first signal SL representing a search bit value from an input search word and inverse search line 306-0 receives a second signal SL representing an inverse of the search bit value. If SL matches DATA and SL matches DATA, the memory cell pair 310-0 will be conductive from A to B. For example, TABLE 1 provided below is a truth table that defines the behavior of any given one of the memory cell pairs 310-0 to 310-M.

TABLE 1 SL SL DATA DATA CONDUCTIVE 0 1 0 1 Yes 0 1 1 0 No 1 0 0 1 No 1 0 1 0 Yes

In TABLE 1. “SL” is a search bit value, “SL” is an inverse of the search bit value, “DATA” is a stored bit value, and “DATA” is an inverse of the stored bit value. As shown, a complementary cell pair is conductive when the search data value matches the stored data value and the inverse of the search data value matches the inverse of the stored data value. In other instances, the memory cell pair 310 is non-conductive because the stored data does not match the search bit.

Returning to FIG. 3, each string in the CAM block 300 stores a data entry and each data bit value in a data entry is mapped to one of the memory cell pairs 310-0 to 310-M in the string. In this way, within each of the complementary memory cell pairs 310 in a string, a first memory cell stores a bit value from the data entry and a second memory cell stores an inverse of the bit value from the data entry.

In an example where the NAND-type flash memory device supports 128 bit strings (i.e., X is 128), the match line 302-0 is connected to memory cells 308-0 to 308-127, which stores 64 bit data entry comprising bit values D_(0,0)-D_(63,63). In this example, bit value D_(0,0) is mapped to memory cell pair 310-0 comprising memory cells 308-0 and 308-1. More specifically, memory cell 308-0 stores the bit value D_(0,0) and the complementary memory cell 308-1 stores D_(0,0), which is the inverse of the bit value D_(0,0).

A search pattern 312 may be input vertically along search lines 304-0 to 304-M and inverse search lines 306-0 to 306-M. More specifically, search lines 304-0 to 304-M receive a first set of voltage signals SL_(0-M) representing a search word 206, and inverse search lines 306-0 to 306-M receive a second set of voltage signals SL _(0-M) representing an inverse of the search word. Input of the search pattern 312 along the search lines causes any string that stores matching data to be conductive because, as discussed above, each individual memory cell pair 310 in the string will be conductive. Because the match lines 302 are precharged, a conductive string allows the match line 302 to discharge. A page buffer 212 connected to a conductive string latches data that indicates a location of matching data (i.e., the search word 206) in the CAM block 300.

The search component 113 outputs an indication of whether a search word 206 is stored by the CAM block 300 and an indicator of the location (e.g., a memory address) of the matching data. In some embodiments, the search component 113 comprises a read-out circuit that reads data from the page buffers 212 of the CAM block 300 to identify the location thereof.

In some embodiments, two page buffers 212 in the CAM block 300 may be tied together to form a serial shift register. Consistent with these embodiments, the search component 113 shifts data out of a first page buffer to a second page buffer and the search component 113 comprises an output compare and counter component to track the number of shifts from one page buffer 210 to the other to identify the location of matching data stored by the CAM block 300.

In some embodiments, two page buffers may be tied together using a single transistor to form a shift register. For example, as shown in FIG. 5, shift register 500 comprises page buffer 502 and page buffer 504 connected by transistor 506.

FIG. 6 is flow diagram illustrating an example method 600 for searching a CAM component in a memory sub-system 110, in accordance with some embodiments of the present disclosure. The method 600 can be performed by processing logic that can include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the method 600 is performed by the search component 113 of FIG. 1. Although processes are shown in a particular sequence or order, unless otherwise specified, the order of the processes can be modified. Thus, the illustrated embodiments should be understood only as examples, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. Additionally, one or more processes can be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are possible.

At operation 605, the processing device receives an input search word. The input search word may be received from a host system (e.g., the host system 120). The input search word comprises a first sequence of M-bits (e.g., “100110101011”).

The processing device generates a search pattern based on the input search word, at operation 610. The search pattern comprises first set of voltage signals representing the search word. That is, the first set of voltage signals represents the first sequence of M-bits. The search pattern further comprises a second set of voltage signals representing a second sequence of M-bits comprising an inverse of the first sequence of bits (e.g., “0110 0101 0100”). Accordingly, in generating the search pattern the processing device generates the second sequence of bits by inverting the input search word and converts the first and second sequence of bits into the first and second signals, respectively. The processing device may alternatively generate a first signal based on the first sequence of bits and generate the second signal by generating an inverse of the first signal. In generating the first and second voltage signals, the processing device may use voltage V_(high) to represent a binary value of “1” and use a voltage V_(low) to represent a binary value of “0” where V_(high) is above a threshold voltage (Vt) and V_(low) is below Vt.

The processing device, at operation 615, provides the search pattern to search lines of a CAM block. The CAM block comprises an array (e.g., a NAND-type flash memory array) of memory cells. The array comprises a plurality of strings and each string in the plurality of strings stores a data entry. A string comprises a plurality of memory cells connected in series between a precharged match line and a page buffer. The match line is precharged in that it is connected to a voltage signal (e.g., representing a logical high state). The CAM block further comprises a plurality of search lines, and each of the memory cells in a string are connected to one of a plurality of search lines.

As noted above, the memory cells in each string are organized as complementary memory cell pairs. Each bit value of a data entry stored by a string is mapped to a complementary memory cell pair in the string. In particular, a first memory cell stores the bit value and the second memory cell stores the inverse of the bit value. More specifically, a first memory cell stores a first charge representing the bit value and the second memory cell stores a second charge representing the inverse of the bit value.

In providing the search pattern to the search lines of the CAM, the processing device provides a first signal representing a search bit value from the first bit sequence to a first search line connected to a first memory cell in a complementary memory cell pair and provides a second search signal representing an inverse of the search bit value to a second search line connected to a second memory cell in the complementary memory cell pair.

If the input search word is stored in the CAM block, input of the search pattern causes the string on which the input search word is stored to become conductive. Because matched lines are precharged, the conductive string allows the match line to discharge. That is, the string conducts a signal resulting from the match line discharging based on the input search word matching the data entry stored on the string connected to the match line. The conductive string provides the signal to a page buffer connected at the other end of the string. The page buffer latches data in response to the signal provided as a result of the match line discharging. The latched data indicates that the match line connected to the page buffer stores a data entry that is identical to the input search word.

The processing device determines whether any matching data is stored by the CAM block (at operation 630). The processing device may determine whether any matching data is stored by the CAM block by reading data from the page buffer of the CAM block.

At operation 625, the processing device determines a location of any matching data stored in the CAM block. That is, the processing device determines the location of a stored data entry that is identical to the input search word. The processing device may determine the location of matching data based on the data read from the page buffer. The location of matching data may comprise one or more memory addresses corresponding to one or more strings within the array.

The processing device, at operation 630, outputs an indication of whether matching data is stored by the CAM block and the location of the matching data. The location of the matching data may, for example, be used to retrieve additional data associated to with the input search word stored by the memory sub-system. The associated data may be stored in a different portion of the memory device on which the CAM block is implemented or on another memory device of the memory sub-system.

EXAMPLES

Example 1 is a system comprising: a memory device comprising a content addressable memory (CAM) block comprising an array of memory cells organized into a plurality of strings, a string in the plurality of strings storing a data entry, the string comprising a plurality of memory cells connected in series between a precharged match line and a page buffer, each of the memory cells connected to one of a plurality of search lines; and a processing device coupled to the memory device, the processing device to perform operations comprising: generating a search pattern based on an input search word comprising a sequence of bits; providing the search pattern as input to the plurality of search lines, the search pattern causing the string to be conductive and provide a signal to the page buffer in response to the input search word matching the data entry stored on the string, the signal resulting from the precharged match line discharging, the page buffer storing data based on the signal; and outputting a location of the data entry within the CAM block based on the data stored by the page buffer.

In Example 2, the plurality of memory cells of Example 1 is optionally configured as a plurality of complementary memory cell pairs and a bit value of the data entry is mapped to a complementary memory cell pair in the plurality of complementary memory cell pairs.

In Example 3, the subject matter of any one of Examples 1 and 2 optionally comprises a complementary memory cell pair comprising: a first memory cell to store a bit value of the data entry, and a second memory cell connected in series with the first memory cell, the second memory cell to store an inverse of the bit value, wherein a first search line in the plurality of search lines is connected to the first memory cell; and wherein a second word line in the plurality of word lines is connected to the second memory cell.

In Example 4, the subject matter of any one of Examples 1-3 optionally comprises a first search line to receive a first search signal representing a search bit value from the input search word, and a second search line to receive a second search signal representing an inverse of the search bit value.

In Example 5, the subject matter of any one of Examples 1-4 optionally comprises determining whether the input search word is stored by the CAM block based on the data stored by the page buffer; and outputting an indication of whether the input search word is stored by the CAM block.

In Example 6, the subject matter of any one of Examples 1-5 optionally comprises reading the data out of the page buffer, the data indicating the location of the string.

In Example 7, the subject matter of any one of the Examples 1-6 optionally comprises the system further comprises: a shift register comprising the page buffer, a second page buffer, and a transistor connected in between the page buffer and the second page buffer, the shift register to serially shift out the data from the page buffer; and a counter to determine the location of the match line by counting a number of shifts performed to serially shift out the data from the page buffer.

In Example 8, the input search word comprises a first sequence of bits, the search pattern comprises a first set of signals representing the input search word and a second set of signals representing a second sequence of bits comprising an inverse of the first sequence of bits, and the subject matter of any one of the Examples 1-7 optionally comprises an inverter to generate the second sequence of bits based on the input search word; and a level shifter to generate the first signal based on the first sequence of bits and to generate the second signal based on the second sequence of bits.

In Example 9, the location of the data entry of any one of Examples 1-8 optionally comprises a memory address of the string within the CAM block.

In Example 10, the memory device of any one of Examples 1-9 optionally comprises a comprises a negative and (NAND)-type flash memory device.

Example 11 is a method comprising receiving, by at least one hardware processor, an input search word comprising a sequence of bits; generating, by at least an inverter and a level selector, a search pattern based on the input search word; providing the search pattern as input to search lines of a content addressable memory (CAM) block, the search pattern causing at least one string in the CAM block to be conductive and provide a signal to a page buffer connected to the string in response to the input search word matching a data entry stored on the string, the signal resulting from a precharged match line discharging along the string; and outputting a location of the data entry within the CAM block based on data read from a page buffer connected to the string, the page buffer storing the data based on the signal resulting from the precharged match line discharging along the string.

In Example 12, the plurality of memory cells of Example 11 is optionally configured as a plurality of complementary memory cell pairs and a bit value of the data entry is mapped to a complementary memory cell pair in the plurality of complementary memory cell pairs.

In Example 13, the subject matter of any one of Examples 11 and 12 optionally comprises a complementary memory cell pair comprising: a first memory cell to store a bit value of the data entry, and a second memory cell connected in series with the first memory cell, the second memory cell to store an inverse of the bit value, wherein a first search line in the plurality of search lines is connected to the first memory cell; and wherein a second word line in the plurality of word lines is connected to the second memory cell.

In Example 14, the providing of the search pattern as input in any one of Examples 11-13 optionally comprises: providing, to the first search line, a first search signal representing a search bit value from the input search word, and providing, to the second search line, a second search signal representing an inverse of the search bit value.

In Example 15, the subject matter of any one of Examples 11-14 optionally comprises determining whether the input search word is stored by the CAM block based on the data stored by the page buffer; and outputting an indication of whether the input search word is stored by the CAM block.

In Example 16, the subject matter of any one of Examples 11-15 optionally comprises determining the location of the data entry by reading the data out of the page buffer, the data indicating the location of the string.

In Example 17, the page buffer of any one of the Examples 11-16 is a first page buffer and the subject matter optionally comprises: serially shifting out the data from the first page buffer to a second page buffer, the first and second page buffer being connected by a transistor; and counting a number of shifts performed to serially shift out the data from the first page buffer.

In Example 18, the sequence of bits is a first sequence of bits, the search pattern comprises a first set of signals representing the input search word and a second set of signals representing a second sequence of bits comprising an inverse of the first sequence of bits; and the generating of the search pattern in any one of Examples 11-17 optionally comprises: inverting the first sequence of bits to generate the second sequence of bits; generating a first voltage signal representing the first sequence of bits; and generating a second voltage signal representing the second sequence of bits.

In Example 19, the location of the data entry of any one of Examples 11-18 optionally comprises a memory address of the string within the CAM block.

Example 20 is A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, configure the processing device to perform operations comprising: receiving an input search word comprising a first sequence of bits; generating a search pattern based on the input search word, the search pattern comprising a first set of signals representing the input search word and a second set of signals representing a second sequence of bits comprising an inverse of the first sequence of bits; providing the search pattern as input to search lines of a content addressable memory (CAM) block, the search pattern causing at least one string in the CAM block to be conductive and provide a signal to a page buffer connected to the string in response to the input search word matching a data entry stored on the string, the signal resulting from a precharged match line discharging along the string; determining a location of the data entry within the CAM block based on data read from the page buffer, the page buffer storing the data based on the signal resulting from the precharged match line discharging; and outputting the location of the data entry within the CAM block.

MACHINE ARCHITECTURE

FIG. 7 illustrates an example machine in the form of a computer system 700 within which a set of instructions, for causing the machine to perform any one or more of the methodologies discussed herein, can be executed. In some embodiments, the computer system 700 can correspond to a host system (e.g., the host system 120 of FIG. 1) that includes, is coupled to, or utilizes a memory sub-system (e.g., the memory sub-system 110 of FIG. 1) or can be used to perform the operations of a controller 115 (e.g., to execute an operating system to perform operations corresponding to the search component 113 of FIG. 1). In alternative embodiments, the machine can be connected (e.g., networked) to other machines in a local area network (LAN), an intranet, an extranet, and/or the Internet. The machine can operate in the capacity of a server or a client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

The machine can be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular telephone, a web appliance, a server, a network router, a switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while a single machine is illustrated, the term “machine” shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

The example computer system 700 includes a processing device 702, a main memory 704 (e.g., ROM, flash memory, DRAM such as SDRAM or Rambus DRAM (RDRAM), etc.), a static memory 707 (e.g., flash memory, static random-access memory (SRAM), etc.), and a data storage system 718, which communicate with each other via a bus 730.

The processing device 702 represents one or more general-purpose processing devices such as a microprocessor, a central processing unit, or the like. More particularly, the processing device 702 can be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, a processor implementing other instruction sets, or processors implementing a combination of instruction sets. The processing device 702 can also be one or more special-purpose processing devices such as an ASIC, an FPGA, a digital signal processor (DSP), a network processor, or the like. The processing device 702 is configured to execute instructions 726 for performing the operations and steps discussed herein. The computer system 700 can further include a network interface device 708 to communicate over a network 720.

The data storage system 718 can include a machine-readable storage medium 724 (also known as a computer-readable medium) on which is stored one or more sets of instructions 727 or software embodying any one or more of the methodologies or functions described herein. The instructions 727 can also reside, completely or at least partially, within the main memory 704 and/or within the processing device 702 during execution thereof by the computer system 700, the main memory 704 and the processing device 702 also constituting machine-readable storage media. The machine-readable storage medium 724, data storage system 718, and/or main memory 704 can correspond to the memory sub-system 110 of FIG. 1.

In one embodiment, the instructions 727 include instructions to implement functionality corresponding to a security component (e.g., the search component 113 of FIG. 1). While the machine-readable storage medium 724 is shown in an example embodiment to be a single medium, the term “machine-readable storage medium” should be taken to include a single medium or multiple media that store the one or more sets of instructions. The term “machine-readable storage medium” shall also be taken to include any medium that is capable of storing or encoding a set of instructions for execution by the machine and that cause the machine to perform any one or more of the methodologies of the present disclosure. The term “machine-readable storage medium” shall accordingly be taken to include, but not be limited to, solid-state memories, optical media, and magnetic media.

Some portions of the preceding detailed descriptions have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the ways used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, conceived to be a self-consistent sequence of operations leading to a desired result. The operations are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure can refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

The present disclosure also relates to an apparatus for performing the operations herein. This apparatus can be specially constructed for the intended purposes, or it can include a general-purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program can be stored in a computer-readable storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks. CD-ROMs, and magnetic-optical disks; ROMs; RAMs; erasable programmable read-only memories (EPROMs); EEPROMs; magnetic or optical cards; or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general-purpose systems can be used with programs in accordance with the teachings herein, or it can prove convenient to construct a more specialized apparatus to perform the method. The structure for a variety of these systems will appear as set forth in the description above. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages can be used to implement the teachings of the disclosure as described herein.

The present disclosure can be provided as a computer program product, or software, that can include a machine-readable medium having stored thereon instructions, which can be used to program a computer system (or other electronic devices) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine-readable (e.g., a computer-readable) storage medium such as a ROM, a RAM, magnetic disk storage media, optical storage media, flash memory devices, and so forth.

In the foregoing specification, embodiments of the disclosure have been described with reference to specific example embodiments thereof. It will be evident that various modifications can be made thereto without departing from the broader spirit and scope of embodiments of the disclosure as set forth in the following claims. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense. 

What is claimed is:
 1. A system comprising: a memory device comprising a content addressable memory (CAM) block; and a processing device coupled to the CAM block, the processing device to perform operations comprising: generating a search pattern based on an input search word, the input search word comprising a first sequence of bits, the search pattern comprising a first signal representing the input search word and a second signal representing a second sequence of hits corresponding to an inverse of the first sequence of bits, the generating of the search pattern comprising: generating a first voltage signal representing the first sequence of bits; and generating a second voltage signal representing the second sequence of bits; providing, as input to search lines of the CAM block, the search pattern, the search pattern causing a string in the CAM block to provide a signal to a page buffer connected to the string in response to the input search word matching a data entry stored on the string, the page buffer storing data based on the signal; and outputting a location of the data entry within the CAM block determined based on a count of a number of shifts performed to serially shift out on the data from the page buffer.
 2. The system of claim 1, wherein: the CAM block comprises an array of memory cells organized into a plurality of strings, a string in the plurality of strings stores the data entry, the string comprising a plurality of memory cells connected in series between a precharged match line and the page buffer, and each of the memory cells connected to one of the search lines.
 3. The system of claim 2, wherein: the search pattern causes the string to be conductive; and the signal is provided by the string based on the precharged match line discharging.
 4. The system of claim 2, wherein: the plurality of memory cells is configured as a plurality of complementary memory cell pairs, and a bit value of the data entry is mapped to a complementary memory cell pair in the plurality of complementary memory cell pairs.
 5. The system of claim 4, wherein: the complementary memory cell pair comprises: a first memory cell to store a hit value of the data entry; a second memory cell connected in series with the first memory cell e second memory cell to store an inverse of the bit, value; a first search line in the plurality of search lines is connected to a gate of the first memory cell; and a second search line in the plurality of search lines is connected to a gate of the second memory cell.
 6. The system of claim 1, wherein the operations further comprise: determining whether the input search word is stored by the CAM block; and outputting an indication of whether the input search word is stored by the CAM block.
 7. The system of claim 1, wherein the system further comprises a read-out circuit configured to read the data out of the page buffer, the data indicating the location of the string.
 8. The system of claim 1, wherein: the processing device comprises: an inverter to generate the second sequence of bits based on the input search word; and a level shifter to generate the first voltage signal and to generate the second voltage signal.
 9. The system of claim 1, wherein: the page buffer is a first page buffer; and the memory device further comprises: a shift register comprising the first page buffer, a second page buffer, and a transistor connected between the first page buffer and the second page buffer, the shift register to serially shift out the data from the page buffer; and a counter to determine the location of the data entry by counting a number of shifts performed to serially shift out the data from the page buffer.
 10. The system of claim 1, wherein the memory device comprises a negative and (NAND)-type flash memory device.
 11. A method comprising: receiving, by at least one hardware processor, an input search word comprising a sequence of bits; generating a search pattern based on an input search word, the input search word comprising a first sequence of bits, the search pattern comprising a first signal representing the input search word and a second signal representing a second sequence of bits corresponding to an inverse of the first sequence of bits, the generating of the search pattern comprising: generating a first voltage signal representing the first sequence of bits; and generating a second voltage signal representing the second sequence of bits: providing, as input to search lines of a content addressable memory (CAM) block, the search pattern, the search pattern causing a string in the CAM block to provide a signal to a page buffer connected to the string in response to the input search word matching a data entry stored on the string; and outputting a location of the data entry within the CAM block determined based on a count of a number of shifts performed to serially shift out on the data from the page buffer.
 12. The method of claim 11, wherein: the CAM block comprises an array of memory cells organized into a plurality of strings, a string in the plurality of strings stores the data entry, the string comprising a plurality of memory cells connected in series between a precharged match line and the page buffer, and each of the memory cells connected to one of the search lines.
 13. The method of claim 12, wherein: the search pattern causes the string to be conductive; and the signal is provided by the string based on the precharged match line discharging.
 14. The method of claim 12, wherein: the plurality of memory cells is configured as a plurality of complementary memory cell pairs, and a bit value of the data entry is mapped to a complementary memory cell pair in the plurality of complementary memory cell pairs.
 15. The method of claim 14, wherein: the complementary memory cell pair comprises: a first memory cell to store a bit value of the data entry; a second memory cell connected in series with the first memory cell, the second memory cell to store an inverse of the bit value; a first search line in the plurality of search lines is connected to a gate of the first memory cell; and a second search line in the plurality of search lines is connected to a gate of the second memory cell.
 16. The method of claim 11, further comprising: determining whether the input search word is stored by the CAM block; and outputting an indication of whether the input search word is stored by the CAM block.
 17. The method of claim 11, further comprising determining the location of the data entry by reading the data out of the page buffer, the data indicating the location of the string.
 18. The method of claim 11, wherein: the generating of the search pattern further comprising: inverting the first sequence of bits to generate the second sequence of bits.
 19. The method of claim 11, wherein the location of the data entry comprises a memory address of the string within the CAM block.
 20. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, configure the processing device to perform operations comprising: receiving, by at least one hardware processor, an input search word comprising a sequence of bits; generating a search pattern based on an input search word, the input search word comprising a first sequence of bits, the search pattern comprising a first signal representing the input search word and a second signal representing a second sequence of bits corresponding to an inverse of the first sequence of bits, the generating of the search pattern comprising: generating a first voltage signal representing the first sequence of bits; and generating a second voltage signal representing the second sequence of bits; providing, as input to search lines of a content addressable memory (CAM) block, the search pattern, the search pattern causing a string in the CAM block to provide a signal to a page buffer connected to the string in response to the input search word matching a data entry stored on the string; and outputting a location of the data entry within the CAM block determined based on a count of a number of shifts performed to serially shift out on the data from the page buffer. 